I know this is way too late for the current PAR, and maybe someone's already turned out all the lights at sv-bc, but I'd appreciate any input on this issue where the LRM appears silent and existing implementations disagree. Consider a module that exports a different task to each of several ports of the same interface.modport type: interface I(); modport mp(export task T()); initial begin $display("interface %m calls T()"); T(); end endinterface : I // module M(I.mp p, I.mp q); task p.T(); $display("called %m through p.T()"); endtask task q.T(); $display("called %m through q.T()"); endtask endmodule : M // module top; I i_p(); I i_q(); M m(i_p.mp, i_q.mp); endmodule : top Is this legal? Depending on your mental model of task export, you might think that each instance of interface I has some sort of reference to the exported task, which itself resides within the module; or, alternatively, you might imagine that the task is effectively rewritten into the body of the interface. If you take the former view (reference-to-task), as one simulator seems to do, then all is well. Its output from the code above is what I would hope for: interface top.i_p calls T() called top.m.p.T through p.T() interface top.i_q calls T() called top.m.q.T through q.T() If you take the latter view (exported task is rewritten into the interface) then the code is illegal because it attempts to write two different tasks T() into the same interface. I can see that this might be a reasonable interpretation if you think of the interface as having an "extern" task declaration; but, in that case, surely the task body should be named interface_name::task_name rather than port_name.task_name Mysteriously, the simulator that complains about this code will accept a slightly altered version in which the exporting module's ports are of generic interface type: module M(interface.mp p, interface.mp q); and it then gives the following output: interface top.i_p calls T() called top.m.T through p.T() interface top.i_q calls T() called top.m.T through q.T() Note the different result from %m within the exported task. I can't make much sense of this. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ This is not just an academic exercise; there are real, useful scenarios in which I need to know what is correct. Other things that might affect the answer, but don't seem to change anything in the two simulators I tried: - having the exported task be "automatic"; - parameterizing the two interface instances differently. Thanks in advance -- Jonathan Bromley Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Sep 10 08:24:44 2008
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