[sv-cc] Re: [sv-bc] query related with event or operator of Verilog-2001.[SPAM]

From: Steven Sharp <sharp_at_.....>
Date: Fri Sep 19 2008 - 11:56:58 PDT
>In LRM 1364.2001, section 4.1 contain a table regarding operator.
>The last row of table shows a operator "or"(event or) but this is not
>present in LRM 1364.2005, section 5.1.

It was removed from that table because it isn't an operator in the
usual sense, and was deemed inappropriate to appear in that table.
That doesn't mean it was removed from the language.  It is still
specified elsewhere.

>module tmp(input in1, in2, output reg out1);
>
>always@(in1 or in2)
>begin
>    out1 = in1;
>end
>endmodule
>
>As most of the standard tool don't show error in for above testcase.

Because it is legal code.


Steven Sharp
sharp@cadence.com


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Received on Fri Sep 19 11:58:52 2008

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