RE: [sv-bc] Question on const declaration RHS

Surya,

A "const" does not affect the RHS of the declaration. Whatever is
allowed for a non-cost variable declaration is allowed for a const. In
fact, a const variable declared inside an automatic block is initialized
every time the block is entered to whatever is the current value of the
RHS expression. It's just that a const variable becomes read-only after
initialization.

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Surya Pratik Saha
> Sent: Tuesday, September 23, 2008 12:45 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] Question on const declaration RHS
> 
> Hi,
> As per SV 1800 LRM, the RHS side of 'const' declaration should be
> consisting of normal const_expression or anything which is already
> declared by another 'const' declaration.
> 
> But consider the e.g. below:
> module top;
>     int x;
>     function int f(input y);
>         x = 1;
>         return f + x;
>     endfunction
>     const int r1 = f(1); // function 'f' is not a constant as it used
a
> global non-parameter variable 'x'
>     const int r2 = x; // 'x' is not declared with 'const'
> endmodule
> 
> Most of the standard simulators pass the case. Is it a bug in the
> simulators? Also OVM package has this type of declaration too which is
> against LRM. Please comment.
> 
> --
> Regards
> Surya
> 
> 
> 
> 
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