Re: [sv-bc] RE: functional if statement

> SystemVerilog added automatic lifetimes to individual modules
> so that all embedded task and function definitions
> have an automatic lifetimes.

A reason this SV feature is little used is that adding the 'automatic' qualifier to a module also changes the lifetime of variables declared in begin-end blocks.

     "An optional qualifier can be used to specify the default lifetime of all variables declared in a task, function, or block defined within a module, interface, package, or program. The lifetime qualifier is automatic or static. The default lifetime is static."

So in such a module, only global variables (or those explicitly declared 'static') hold their values across iterations of an always procedure.

-- Brad



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