> Fortunately or unfortunately, as long as the function > did not depend on a held value, it behaved like a correct piece of > combinational logic, which means that there is plenty of legacy code > with Verilog-1995 static functions that are correctly coded, so for > legacy-code reasons we can't just ask synthesis tools to reject > static functions in RTL code :-( But surely it would be a *very* good idea for synthesis to choke on any static function unless it represents combinational logic (i.e. it's a pure function in the mathematical, not the OOP, sense). Ask any half-decent VHDL RTL designer to give up using functions and they will laugh you out of town. Let's by all means have a campaign to get Verilog RTL folk to use automatic functions exclusively, but I can't live with a global recommendation to avoid functions altogether. Afterthought: We have missed some good opportunities in SV to legislate for the use of synthesis-friendly idioms within the new RTL always blocks. For example, it would be rather reasonable to have the language outlaw any call to a static subprogram from within an always_??? block. I think users would see that sort of thing as a positive advantage. -- Jonathan Bromley Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Dec 10 14:24:10 2008
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