RE: [sv-bc] Question on mandatory "static" to declare intent

Hi,

I agree with your question.

This example was added by Mantis 1556. I wanted to look at intermediate versions of that proposal. Unfortunately I did not keep them.

I will strengthen your question by noting that the example preceding this text shows a declaration of an automatic variable inside an initial block:

module msl;
	int st0; // static
	initial begin
		int st1; // static
		static int st2; // static
		automatic int auto1; // automatic 
 
Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of David Jones
> Sent: Monday, December 29, 2008 12:38 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] Question on mandatory "static" to declare intent
> 
> (Apologies if this comes too late)
> 
> I have a question from P1800/D8. Part of section 6.21 
> describes the conditions under which use of the "static" 
> keyword is mandatory to confirm intent, where its use would 
> otherwise be redundant.  In the examples we have:
> 
> int svar1 = 1; // static keyword optional initial begin
>   int svar2 = 2; // static keyword optional
>   ...
> 
> module top_illegal; // should not compile initial begin
>   for (int i=0; i<3; i++) begin
>     int loop3 = 0; // illegal statement
>     ...
> 
> The question: why is "static" optional on svar2? It will be 
> optional if it is illegal to declare svar2 as automatic. But 
> I see no text making it illegal to do so. In this example 
> it's pointless, as one can prove that an automatic svar2 
> would be initialized only once. But is there any difference between:
> 
> initial begin
>   int var1 = ...; // In theory static is optional ...
> end
> 
> always begin
>   int var2 = ...; // ???
>   ...
>   #10;
> end
> 
> I might want to have var2 initialized each time through the "always"
> block, and therefore I ought to declare it automatic. But is 
> this not the same situation as with the static block and 
> var1?  At least two commercial simulators accept automatic 
> definitions inside both "initial begin" and "always begin" blocks.
> 
> Interestingly, one of the tools I've tried accepts:
> 
> initial begin
>   int i = 1;
> ...
> 
> But rejects:
> 
> always begin
>   int i = 1;
> ...
> 
> From a usability standpoint I agree with the tool's decision 
> to reject the latter. However, that doesn't jibe with a 
> literal interpretation of the LRM text. Since it is not 
> illegal to declare the variable as automatic in either case 
> (but in the "initial" case it may be
> pointless) the "static" should be mandatory in both cases.
> 
> Perhaps the clause stating:
> 
> "The static keyword shall be optional where it would not be 
> legal to declare the variables as automatic"
> 
> should be reworded as:
> 
> "The static keyword shall be optional where the compiler can 
> determine that initialization can occur at most once 
> regardless of the intended lifetime of the variable."
> 
> And if this has to wait for Verilog-2012 then so be it.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.