RE: [sv-bc] Question on mandatory "static" to declare intent

> -----Original Message-----
> From: David Jones [mailto:djones@xtreme-eda.com]
> Hmmm... we're quickly going down a rathole.
> 
> Is the following legal?
> 
> > module top;
> > int A = 1;
> > initial begin
> >   int B = 5; // ???
> > end
> > endmodule

This should not be legal. I've filed mantis 2550 to log the LRM example
error.

The result of the LRM text rule is simple: if you have a choice of
lifetime where the default is static, you must use a lifetime keyword
with an initialization. 

There are many other cases where user experience has shown that these
types of syntactic restriction are very useful even though they appear
redundant. The required extra set of parenthesis around an assignment
within a expression is another good example. 

'if (A=B) ...' is not legal because this is more likely (99%) to be a
typo than the user's intent AND very difficult to detect/debug.

As a Hardware Description Language, we owe it to the users to provide
simple mechanisms that clearly express their intent where it would
otherwise be ambiguous and difficult to debug.

Dave

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