[sv-bc] Hierarchical reference of covergroup formal argument

Hi,
Is it not allowed to refer covergroup formal argument hierarchically 
like task/function formal argument? For example:

module top;
covergroup cg ( input int x , int y, int c);
d: coverpoint x;
endgroup
initial begin:b
    cg c_g;
    c_g.y = 1; // is it not allowed
end
endmodule

I did not see anything mentioned in the LRM, though some of the standard 
simulators fail for that.

-- 
Regards
Surya




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