RE: [sv-bc] output_terminal ::= net_lvalue

I'm not sure. The difference in the text in Clause 6, for example, between nets and variables looks deliberate to me. A difference between output ports and output terminals is that output ports are equivalent to continuous assignments. That is not true for output terminals.

Shalom

________________________________
From: Rich, Dave [mailto:Dave_Rich@mentor.com]
Sent: Thursday, January 15, 2009 5:49 PM
To: Bresticker, Shalom; Daniel Mlynek; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] output_terminal ::= net_lvalue

probably left over from Verilog. 1364 LRM

________________________________
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, January 15, 2009 6:32 AM
To: Daniel Mlynek; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] output_terminal ::= net_lvalue

4.9.6 also says that primitive output terminals must be connected to nets, not variables. I don't know what the reason is.

Shalom

________________________________
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Daniel Mlynek
Sent: Thursday, January 15, 2009 4:11 PM
To: sv-bc@server.eda-stds.org
Subject: [sv-bc] output_terminal ::= net_lvalue
LRM for gate instantation have :
output_terminal ::= net_lvalue

Above forbids to use variable on output ports - this is intentional restriction - or variables should be allowed on output gate terminals?


DANiel

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