[sv-bc] extending on port connection, continous assign

For connection via ports and conitnous assignment where we have differenct
sizes and source need to be extended in this cases sign extension rules
takes place (same as for BA = and NBA <=)? Or unconnected bits remain Z? See
below example 
 
module buff (input wire [31:0] in1, output wire [31:0] out1);
 assign
  out1 = in1;
 
endmodule
 
module top;
  int in1;
 
 wire out1;
 wire [114:0] out2;
 wire [114:0] out3;
 
 buff uut1 (.in1(in1),.out1(out2));  
 assign out3 = in1;
 initial begin
  in1 =-1;
 #1;
 $display("%b", out2);
 $display("%b", out3);
 end
 
endmodule
 
 
Results should be:

 
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
zzzzzzz11111111111111111111111111111111
 
1111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
or
 
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
zzzzzzz11111111111111111111111111111111
 
zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
zzzzzzz11111111111111111111111111111111
or 
 
1111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
 
1111111111111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111
or
0000000000000000000000000000000000000000000000000000000000000000000000000000
000000011111111111111111111111111111111
0000000000000000000000000000000000000000000000000000000000000000000000000000
000000011111111111111111111111111111111
 
DANiel

 



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