[sv-bc] RE: [sv-ec] Question about interface ports on modules

Francoise,
Michael,

There is no problem have an interface instance at the top level, The
issue is there no way to connect the port of a top level instance,
regardless of whether the port is an interface or regular signal.

From my simulation P.O.V., the synthesis flow is the same as the
separate compilation use model for simulation. So what it does in the
absence of port connections at the top level is a tool issue. I do
believe synthesis tools do require specifying what would have been
connected to an interface port outside the language.


-----Original Message-----
From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Francoise Martinolle
Sent: Wednesday, April 15, 2009 10:28 AM
To: Michael Burns; sv-ec@server.eda.org
Subject: RE: [sv-ec] Question about interface ports on modules


 Michael,

I remember that the connection of a interface instance at a higher level
of hierarchy
was written to make connection to an interface instance at a lower level
of hierarchy illegal.
I think that interfaces which are top level should be allowed. That is
my opinion.
However the LRM makes implicit instantiation of interfaces illegal :
only modules and
programs can be implicitly instantiated as top levels.

In section 25.3:
================
Interfaces can be declared and instantiated in modules (either flat or
hierarchical), but modules can neither
be declared nor instantiated in interfaces. In contrast to modules (see
23.3) and programs (see 24.3), interfaces
are never implicitly instantiated.

Francoise
    '

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Michael Burns
Sent: Wednesday, April 15, 2009 1:15 PM
To: sv-ec@eda.org
Subject: [sv-ec] Question about interface ports on modules


Hi folks,

There is a restriction in 23.3.3.4 (that has been around since Accellera
SV) that any interface ports of a module must be connected to an
interface instance at a higher level of hierarchy. This would seem to
preclude creating an RTL design with interface ports at the top level.
What is the reason for this restriction? Am I misunderstanding the
meaning here?

More specifically, for simulation one would normally have a testbench
that instantiates the DUT and connects the interface ports - no problem
there. However, many other tools (synthesis, formal, back-end, etc.)
read in just the DUT. Would those tools be required to reject a design
with top-level interface ports?

Thanks,
Mike


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