RE: [sv-bc] Implicit generate block for loop construct inside conditional construct

You understand correctly.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha
> Sent: Wednesday, April 22, 2009 11:05 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] Implicit generate block for loop construct 
> inside conditional construct
> 
> Hi,
> If we consider the case:
> module top;
>     if (1) // Will it create an implicit named block or not
>         for (genvar g = 1; g < 10; g++)
>             reg x;
>         end
>     int b;
> endmodule
> 
> LRM mentioned for conditional construct directly nested 
> inside another conditional construct does not create separate 
> scope. I think then looping construct directly nested inside 
> another conditional construct should create then a separate 
> scope. Can you please confirm. If the answer is yes, then 
> also for that block, name will be generated as per name 
> generation scheme for unnamed generate block mentioned in the LRM.
> 
> --
> Regards
> Surya
> 
> 
> 
> 
> -- 
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