RE: [sv-bc] Implicit generate block for loop construct inside conditional construct

Daniel,

This is a Verilog-2005 enhancement.  See the attachments in

   http://boydtechinc.com/etf/archive/etf_2004/2566.html

My experience is that most designers don't want to omit the begin-end, and my opinion is that they'd be safer not to.

-- Brad


________________________________
From: owner-sv-bc@eda.org [owner-sv-bc@eda.org] On Behalf Of Surya Pratik Saha [spsaha@cal.interrasystems.com]
Sent: Wednesday, April 22, 2009 2:35 AM
To: Daniel Mlynek
Cc: 'Bresticker, Shalom'; 'sv-bc@eda.org'
Subject: Re: [sv-bc] Implicit generate block for loop construct inside conditional construct

No Daniel. As per LRM, if begin-end is missing for loop generate construct, an implicit begin-end scope is created.

Regards
Surya



-------- Original Message  --------
Subject: Re:[sv-bc] Implicit generate block for loop construct inside conditional construct
From: Daniel Mlynek <daniel.mlynek@aldec.com><mailto:daniel.mlynek@aldec.com>
To: 'Bresticker, Shalom' <shalom.bresticker@intel.com><mailto:shalom.bresticker@intel.com>, 'Surya Pratik Saha' <spsaha@cal.interrasystems.com><mailto:spsaha@cal.interrasystems.com>, 'sv-bc@eda.org<mailto:sv-bc@eda.org>' <sv-bc@eda.org><mailto:sv-bc@eda.org>
Date: Wednesday, April 22, 2009 3:02:02 PM

Is there begin missing inside for loop - as far as I know this begin end in
generate for loop is obligatory:

 module top;
     if (1) // Will it create an implicit named block or not
         for (genvar g = 1; g < 10; g++) begin
             reg x;
         end
     int b;
 endmodule

-----Original Message-----
From: owner-sv-bc@server.eda.org<mailto:owner-sv-bc@server.eda.org> [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: 22 kwietnia 2009 10:15
To: Surya Pratik Saha; sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: RE: [sv-bc] Implicit generate block for loop construct inside
conditional construct

You understand correctly.

Shalom



-----Original Message-----
From: owner-sv-bc@server.eda.org<mailto:owner-sv-bc@server.eda.org>
[mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha
Sent: Wednesday, April 22, 2009 11:05 AM
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] Implicit generate block for loop construct inside
conditional construct

Hi,
If we consider the case:
module top;
    if (1) // Will it create an implicit named block or not
        for (genvar g = 1; g < 10; g++)
            reg x;
        end
    int b;
endmodule

LRM mentioned for conditional construct directly nested inside another
conditional construct does not create separate scope. I think then
looping construct directly nested inside another conditional construct
should create then a separate scope. Can you please confirm. If the
answer is yes, then also for that block, name will be generated as per
name generation scheme for unnamed generate block mentioned in the
LRM.

--
Regards
Surya




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