RE: [sv-bc] Class constructor with non-ANSI style port

For constancy, I rather not see non-ANSI style ports/arguments anywhere.
It's only for legacy Verilog-11995. And you certainly can't have
non-ANSI style arguments in an extern prototype.

Dave


-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Saturday, April 25, 2009 8:34 AM
To: sv-ec@eda.org
Cc: sv-bc@eda.org
Subject: RE: [sv-bc] Class constructor with non-ANSI style port

Surya,

I don't recall any deep reason for the restriction, but it's not an
accident.  Does anyone actually want to declare class constructors with
the antique flair of Verilog-1995?  For example, the restriction was not
listed by Jamie in

     http://www.eda.org/sv-ec/hm/1687.html

For the evolution of this part of the BNF see the attachments in the
following

     http://www.eda.org/sv-ec/hm/1611.html
     http://www.eda.org/sv-ec/hm/1622.html
     http://www.eda.org/sv-ec/hm/1714.html

I can see how, for consistency, enhancing the copy constructor to allow
old-style port declarations makes sense, yet if that enhancement were
made, I don't think it would change how people actually write class
constructors.

-- Brad


________________________________________
From: owner-sv-bc@eda.org [owner-sv-bc@eda.org] On Behalf Of Surya
Pratik Saha [spsaha@cal.interrasystems.com]
Sent: Saturday, April 25, 2009 4:10 AM
To: sv-bc@eda.org
Subject: [sv-bc] Class constructor with non-ANSI style port

Hi,
Current BNF does not allow non-ANSI style port declaration inside class
constructor.
Is there any reason not to allow it. For the following e.g.

module top;
    class C;
        int x;
        function new;
            input y;
            int y;
            x = y;
        endfunction
    endclass
    C x = new(1);
endmodule

Different simulators behave differently (some pass, some fail).

--
Regards
Surya




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