RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

>I assume that the intent was to consider the latter three separate but the first block as a single example.

Just a typo, written quickly.  Didn't mean to repeat 'in' 3x.  Not part of the actual proposal.

According to 6.22

  "SystemVerilog does not require a category for identical types to be defined here because there is no construct in the SystemVerilog language that requires it."

-- Brad



-----Original Message-----
From: Gordon Vreugdenhil [mailto:gordonv@model.com]
Sent: Tuesday, April 28, 2009 7:36 AM
To: Brad Pierce
Cc: sv-bc@eda.org
Subject: Re: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)


I don't particular like the word "identical" in that sentence
(the old or the new one).  That has already caused some
issues in class function prototypes; is "T" identical to
"int" if we have "typedef int T;" ?

Is there any reason to not say

    Aside from the signed attribute mentioned below, the data
    types between the two declarations of a port shall match.

That takes away any uncertainty as to whether different
typedefs (or type parameters, etc) can be used to define
the types.  It is only the final resolution of the type
that counts.

In addition, I am confused by Brad's example.  Certainly
"in" cannot be declared three times.  I assume that the
intent was to consider the latter three separate but the first
block as a single example.

I'd like to make sure as well that we agree as to *why* the
first example block is illegal.  "in1" is illegal since the
resulting type of "bit" is not legal for a net; "in1" is
implicitly a net type since "var" is not specified and it
is an input.  "in2" is illegal since the type "T" is a
packed [1:5] meaning that the "T [1:10] in2" does not have
the same packed dimensions as "input [1:10] in2" which is
not legal.  If, however, "T" was just "typedef logic T;",
I would consider that to be legal even though the data
types are not "identical" (the implicit datatype matches
T in this case, but what does "identical" even mean?).

Gord.

Brad Pierce wrote:
> Following up to http://www.eda-stds.org/sv-bc/hm/8973.html ,
 > which became Mantis item http://www.eda-stds.org/svdb/view.php?id=2593 ,
 > which became ballot comment #4, Steven Sharp has uploaded a proposal
 > that would clarify that the following declarations are illegal
>
>     input [5:0] in1;
>     bit [5:0] in1;
>
>     typedef logic [1:5] T;
>     input [1:10] in2;
>     T [1:10] in2; // 1 to 5 varies most rapidly
>
> But the following declarations would still be legal
>
>     input var bit [5:0] in; // input variable
>     input T [5:0] in;       // input net
>     input var T [1:10] in;  // input variable
>
> -- Brad
>
>
>

--
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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