[sv-bc] query: padding in verilog95/v2k

Hi,

 

I need to know what would be netlist in below testcase in all 3 verilog
version(verilog95,v2k,systemverilog):

 

module cr50401_z_padding (O0, O1, D0, D1, cond0, cond1);

input [0:67] D0, D1;

output [0:67] O0, O1;

input cond0, cond1;

    assign O0 = cond0 ? D0 : 'bz; // All 64 bits should have a tristate
driver

    assign O1 = cond1 ? D1 : 32'bz; // Top 32 bits will not have
tristate driver

endmodule

 

1)verilog95

2)verilog2000

3)system verilog

 

Is there any difference functionally for testcase in above 3 above
mentioned languages ? Is padding in verilog95 and v2k/sysverilog
different if bit width is greater than 32?

 

Regards,

Prakash


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