[sv-bc] RE: query: padding in verilog95/v2k

Hi Shalom,

 

Thanks for reply.

I need one more clarification:

 

NOTE-In IEEE Std 1364-1995, in unsized literal constants where the
high-order bit is unknown or three-state, the x or z was only extended
to 32 bits."

Should 0 be padded in verilog95 after 32 bits when high order bit is
unknown/three state? 

 

Regards,

Prakash

________________________________

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Wednesday, May 06, 2009 3:48 PM
To: Prakash Barnwal; sv-bc@server.eda.org
Cc: sv-ec@server.eda.org
Subject: RE: query: padding in verilog95/v2k

 

The V2K/SV LRM says,

"Unsized unsigned literal constants where the high-order bit is unknown
(X or x) or three-state (Z or z) shall be extended to the size of the
expression containing the literal constant.

NOTE-In IEEE Std 1364-1995, in unsized literal constants where the
high-order bit is unknown or three-state, the x or z was only extended
to 32 bits."

Thus, 'bz would have only 32 z bits in Verilog-1995. But I don't think
anyone actually wants that behavior. 

This was corrected in Verilog-2001.

 

Shalom

 

 

 

	
________________________________


	From: owner-sv-ec@server.eda.org
[mailto:owner-sv-ec@server.eda.org] On Behalf Of Prakash Barnwal
	Sent: Wednesday, May 06, 2009 1:02 PM
	To: sv-bc@server.eda.org
	Cc: sv-ec@server.eda.org
	Subject: [sv-ec] query: padding in verilog95/v2k

	Hi,

	 

	I need to know what would be netlist in below testcase in all 3
verilog version(verilog95,v2k,systemverilog):

	 

	module cr50401_z_padding (O0, O1, D0, D1, cond0, cond1);

	input [0:67] D0, D1;

	output [0:67] O0, O1;

	input cond0, cond1;

	    assign O0 = cond0 ? D0 : 'bz; // All 64 bits should have a
tristate driver

	    assign O1 = cond1 ? D1 : 32'bz; // Top 32 bits will not have
tristate driver

	endmodule

	 

	1)verilog95

	2)verilog2000

	3)system verilog

	 

	Is there any difference functionally for testcase in above 3
above mentioned languages ? Is padding in verilog95 and v2k/sysverilog
different if bit width is greater than 32?

	 

	Regards,

	Prakash

	
	-- 
	This message has been scanned for viruses and 
	dangerous content by MailScanner <http://www.mailscanner.info/>
, and is 
	believed to be clean. 

---------------------------------------------------------------------
Intel Israel (74) Limited
 
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.