RE: [sv-bc] Re: Mandated warnings

From: Arturo Salz <Arturo.Salz_at_.....>
Date: Thu May 07 2009 - 13:36:23 PDT
I've changed the subject of this message to reflect the true thread.

Given that simulators must implement bounds checking (in order to ignore a write) regardless of whether built-in out-of-bounds assertions are enabled or disabled, the performance impact of checking the out-of-bounds condition is almost nil. If a compiler can optimize away the bounds-check then surely it can optimize the assertion as well.

I agree with Steven that there is an increasing performance impact when assertions do occur, when tools must check whether to issue an assertion, whether the assertion is temporarily on or off, or whether the assertion should be issued immediately or deferred. In addition, these assertions will also impact memory and run-time of both compilation and simulation due to the additional information that must be maintained in order to be able to issue meaningful (user actionable) assertions. This information may include the source location, the array name, the offending indexes, etc... This is certainly a non-trivial change and possibly one of the reasons for vendor trepidation.

I would advise we stir away from changing the semantics along the lines suggested by Brad because that could indeed have a large impact on simulation as well as debug. Plus, simply setting the memory to X might be too pessimistic since actual hardware behavior will likely depend on the existing value stored in the array and the new value being written - not just the index. Finally, as Greg pointed out, X'ing an entire memory due to a glitch in signal propagation would be very pessimistic and cause a huge debug problem. I imagine that such a change in behavior with no tracing mechanism would make such a feature largely useless.

        Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Steven Sharp
Sent: Thursday, May 07, 2009 11:52 AM
To: gordonv@Model.com; shalom.bresticker@intel.com; Stephen.Hill@arm.com
Cc: jonathan.bromley@doulos.com; sv-ec@eda.org; sv-bc@eda.org; Stephen.Hill@arm.com
Subject: RE: [sv-bc] Re: Mandated warnings -- was Re: [sv-ec] Mantis 2701, ballot ID #44 - Arturo's feedback

I am very sympathetic to the user arguments here.  I think the performance
impact of such checking is relatively small.

My main concern is the possibility of large amounts of existing code that
does this already, particularly at initialization.  Many of our customers
might be very unhappy if we suddenly started spewing warnings on working
designs.

The possibility of standard mechanisms to turn off the warnings has been
suggested, but that needs more LRM work than is appropriate at this stage
of the process.  We don't even know at this point how detailed that control
needs to be.  If it has to be on a per-instance basis, and turned on or
off during particular times, then it gets a lot more complex.

Steven Sharp
sharp@cadence.com


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Received on Thu May 7 13:37:19 2009

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