Hi, Greg. Thinking about Stephan's suggestion led me (a synthesis guy) to wonder about how simulation would treat either a warning, error, or an assertion for out-of-bounds in the case where the index value (typically a multibit bus) behaves in a "glitchy" manner? As I tried to imagine an assertion to do this job , the question of Immediate vs Deferred Immediate semantics emerged, which led to my current question. Do glitchy index values ever corrupt a simulation? [SB] Yes, glitchy writes are a big problem. Glitchy reads are usually much less of a problem, though in certain cases they can be problems also, such as when reading an interrupt or status bit clears the bit. Regards, Shalom --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri May 8 06:05:45 2009
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