[sv-bc] RE: [sv-ec] Case @*

However, in this particular example, the question is whether there would be
an initial change in i that triggers the always procedures. 
OK so we can change the code by adding #0 : "initial #0 i = 0;"
This also occured in OVL and was reported in Mantis 2174 and 2426, the
latter filed by you.
Yes that is true - I just wanted to fwd this issue to commitee as I hit this
one once again - maybe correct behaviour can be explained in LRM as user
have problems with such codes
 
DANiel

  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: 19 maja 2009 10:02
To: Daniel Mlynek; sv-ec@server.eda.org
Cc: sv-bc@server.eda.org
Subject: RE: [sv-ec] Case @* 


Hi, Daniel.
 
You are correct. A strict interpretation of the LRM makes the implicit
sensitivity list include i.
 
However, in this particular example, the question is whether there would be
an initial change in i that triggers the always procedures. That depends on
whether the initial procedure executes before or after the always procedures
are initiated. The LRM does not define an order.
 
Your example also demonstrates a "gotcha" of always @* that can cause
simulations to enter an inifinite loop. This is documented in my paper at
http://www.scribd.com/doc/14210222/Return-of-the-SystemVerilog-Gotchasbresti
cker. Some of the simulation vendors have also documented this behavior. I
have seen this occur more than once.
 
This also occured in OVL and was reported in Mantis 2174 and 2426, the
latter filed by you.
 
SV has solved this gotcha in always_comb by excluding such variables from
the implicit sensitivity list. This is one of the advantages of always_comb
over always @*.
 
As a result of this gotcha, some vendors have started excluding such
variables from the implicit sensitivity list of always @* anyway, like
always_comb, as this is the desirable behavior.
 
Regards,
Shalom


  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Daniel Mlynek
Sent: Tuesday, May 19, 2009 9:56 AM
To: sv-ec@server.eda.org
Subject: [sv-ec] Case @*

in their libs is using code patterns like below (it was simplified in order
to show the root of the problem):


module top;
 
integer i;
 
initial i = 0;
 
always @(*)
    for (i = 0; i < 10; i++)
    begin
        $display("1 ", i);
    end
 
always @(*)
    for (i = 0; i < 10; i++)
    begin
        $display("2", i);
    end
 
endmodule

 
The intention is that alwayses in above code  should be in-sensitive for
changes of "i" - so nothing should be printed. I've analysed the LRM in
context of above code and IMHO according to LRM alwayses should be
sensivitve to i changes - as this is global variable readed in in both those
process. There is no such rule in LRM that for loop index variable should be
exluded from implicit sensitivity list.
 
Could you please take a look on above and point me how should it work and
where is it described in LRM - or the author intention was wrong and code
should be rewritten using local index variables in for loop?
 
 
DANiel

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