RE: [sv-bc] Hierarchical names and hierarchical references

I think that a hierarchical reference is the use of a hierarchical name.

Shalom

________________________________
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
Sent: Sunday, June 07, 2009 10:20 AM
To: sv-bc@eda.org
Subject: RE: [sv-bc] Hierarchical names and hierarchical references

Surya,

According to 13.3.1, "Automatic task items cannot be accessed by hierarchical references. Automatic tasks can be invoked through use of their hierarchical name." This seems to be making some distinction between hierarchical "reference" and hierarchical "name", but I don't know what it is.

Your example is syntactically illegal as written, because the declarations of the data objects "t1" and "ti2" need to begin either with the 'var' keyword or a net type keyword.  See footnote 13 in A.10.

-- Brad



From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Surya Pratik Saha
Sent: Wednesday, June 03, 2009 10:56 PM
To: sv-bc@eda.org
Subject: [sv-bc] Hierarchical names and hierarchical references

Hi,
In SV 2009 draft 7a LRM, in many number places there are references of "hierarchical names" and "hierarchical references". I hope the meaning are same. Please confirm.

Now in "Type operator" section (6.23), it is mentioned:
The expression shall not be evaluated and shall not contain any hierarchical references or references to elements of dynamic objects.

If we consider "hierarchical names" and "hierarchical references" have same meaning, then following e.g. should be illegal
module top;
   type (ta.s.x) t1; // First identifier is not yet defined, so it is hierarchical name
   type (s.x) ti2; // First identifier is not yet defined, so it is hierarchical name
   struct {int x;} s;
       task ta;
           struct {int x;} s;
       endtask
endmodule

But some standard simulators support this. So please let me know if my understanding is incorrect.


--

Regards

Surya

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