The Annex footnote is a too far away from the appropriate text to be very useful or even noticed. I believe the proposed friendly amendment solves the problem. Thanks, Brad for pointing this out. Regards - Cliff At 11:30 AM 6/7/2009, Brad Pierce wrote: > > SVDB 2667 - No > >Also, as noted in bugnote 8449, the following parameter assignment >is illegal according to footnote 18 > > parameter type T2; > >-- Brad >... > >SVDB 2677 - No >Proposed friendly amendment >http://www.eda.org/svdb/view.php?id=2677 > >When I first read the proposed wording, it looked like the forward >typedef could be in an earlier scope or in a later scope ("scope >either before or after the final type definition"). Add "same" and a >comma after "scope" and the ambiguity goes away. > >WAS: >... It shall be legal to have a forward type declaration in the scope >either before or after the final type definition. > >PROPSED: >... It shall be legal to have a forward type declaration in the same >scope, either before or after the final type definition. > >If I understand the proposal correctly, it just says you can have as >many forward typedefs in a scope and put them anywhere, although the >practice seems faulty and confusing to me. It only allows for one >final type definition, which is then applied to all forward typedefs, >wherever they might be placed within the same scope. Is this correct? ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jun 7 12:08:53 2009
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