RE: [sv-bc] Interesting .* port connection ambiguity

The LRM requires that the names match, but the data types need only be equivalent.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Clifford E. Cummings
> Sent: Wednesday, June 17, 2009 6:49 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] Interesting .* port connection ambiguity
> 
> Hi, All -
> 
> While teaching a class this week, someone asked the question about 
> ports connected to buses with the same name and size, but different 
> indices and reversed indices.
> 
> For example, look at alu_accum5 module example just before clause 
> 23.3.3 in the ballot draft. If you change the declaration for the 
> alu_out wire bus to:
> wire [1:8] alu_out;
> There are at least two implementations that make the .* connections 
> and simulate the design just fine.
> 
> I don't know if we said whether or not this was legal or whether or 
> not it should even be legal. The alu_out bus does match in name and 
> size, so I guess it is legal. Is there any reason it should not be 
> legal? Have we adequately described this possibility in the LRM? Too 
> late to update now but we could put it into our Mantis todo list.
> 
> Regards - Cliff
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
> 
> 
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