RE: [sv-bc] rules for interface module port used in nested instantation as port for another module

I agree with your interpretation, except as noted below:

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Daniel Mlynek
Sent: Monday, July 13, 2009 2:44 AM
To: sv-bc@server.eda.org
Cc: sv-ec@server.eda.org
Subject: [sv-bc] rules for interface module port used in nested
instantation as port for another module

 

I've doubts for below sample. I haven't found in LRM rules for conecting
interface port to module instantation. Can anyone take a look a responce
to my doubts:

	interface iface;
	 reg r; 
	 reg r1;
	 modport slave (input r);
	 modport master(input r1);
	endinterface

	 

	module top;
	 iface if_();
	 sub uut(if_.slave);
	endmodule

	 

	module sub(iface if_);
	 sub1 uut1(if_.slave);// dillowed?  imho forbidden as this is
already slave[DR]  This should be OK as it is redundant.
	 sub1 uut2(if_.master);// dillowed? imho forbidden as from slave
we do not have access to master
	 sub1 uut3(if_);// if_ here is restricted with slave modport so
in uut3 there will be also slave mopdort in use 
	endmodule

	 

	module sub1(iface if_);
	endmodule

DANiel


 


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