[sv-bc] Mantis 2396 - Edge event for DDR logic

Hi, All -

I just noticed Mantis 2396 passed by the SV-SC that introduced the 
@(edge clk) syntax.

I know we talked about this in the BC but I did not realize that this 
was taken up in a more complete form by the SV-SC.

We designers wanted the @(edge clk or negedge rst_n) syntax to define 
DDR flip-flops. Looks like we got it by way of the SV-SC. Since I 
missed it before, I wanted to make sure this is indeed passed and 
should be presented in the update presentation next week at DAC(?)

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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