Hi,
In SV 2009 draft 7a LRM, section 6.22.2 Equivalent types, there is a
big example explaining type compatibility rules in SV. It mentions some
rule numbers also, but it is not clear which rule it tries to point
out. Also the last assignment as given below marked as illegal, but it
is not clear why.
s1.v5 = s2.v5; // illegal - types from s1 and s2
(rule 4)
BTW, none of the standard simulators or synthesis tool fail for the
case. I think LRM should correct it.
--
Regards
Surya
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Received on Wed Aug 5 06:51:44 2009