RE: [sv-bc] Array query functions on interface port and instance array

From: Mark Hartoog <Mark.Hartoog_at_.....>
Date: Thu Aug 13 2009 - 10:16:09 PDT
Yes, but an interface or an instance is not a data type.

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Thursday, August 13, 2009 3:48 AM
To: Surya Pratik Saha
Cc: sv-bc@eda.org; Sourasis Das
Subject: RE: [sv-bc] Array query functions on interface port and instance array

7.4 says,

"Unpacked arrays are formed from any data type"
Shalom


________________________________
From: Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com]
Sent: Thursday, August 13, 2009 12:57 PM
To: Bresticker, Shalom
Cc: sv-bc@eda.org; Sourasis Das
Subject: Re: [sv-bc] Array query functions on interface port and instance array
Hi Shalom,
But I don't see any reference in the LRM that allows array query functions on interface port or instance array. Unapacked array section does not include interface port or instance array. Please help me if I miss any part in the LRM.


Regards

Surya


-------- Original Message  --------
Subject: Re:[sv-bc] Array query functions on interface port and instance array
From: Bresticker, Shalom <shalom.bresticker@intel.com><mailto:shalom.bresticker@intel.com>
To: Surya Pratik Saha <spsaha@cal.interrasystems.com><mailto:spsaha@cal.interrasystems.com>, sv-bc@eda.org<mailto:sv-bc@eda.org> <sv-bc@eda.org><mailto:sv-bc@eda.org>
Cc: Sourasis Das <sourasis@cal.interrasystems.com><mailto:sourasis@cal.interrasystems.com>
Date: Thursday, August 13, 2009 3:20:44 PM


Your failures seem to be tool limitations, not language restrictions.



Shalom







SV 2009 draft 7a LRM has described array query functions in

"20.7 Array

querying functions" which uses reference of clause 7 where

the unpacked

array is defined. The clause 7 defines unpacked arrays of

different data

types. But it is not clear what will be the expected behavior

of array

query functions if they are applied on instance array of

interface port

array. For the following case what will be the expected behavior?



interface a;

endinterface

module test(in1,in2,out);

input [7:0] in1,in2;

output reg [7:0]out;



a a[3:0]();

assign out = $size(a);

bottom inst(a);

endmodule



module bottom(a a[4]);

byte out;

assign out = $size(a);

endmodule



Some simulators fail and some pass for the above case.



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