[sv-bc] Expression evaluation question

Hi,

 

What should be the proper result for the example below?

 

module test;

 

  bit [15:0] s;

  reg [15:0] a, b;

 

  initial

    begin

      a = 16'hxx15;

      b = 16'h1234;

      s = a + b;

      $display("s:%h", s);

      s = 16'hxx15 + 16'h1234;

      $display("s:%h", s);

    end

 

endmodule

 

One commercial simulator is giving:

 

s:1249

s:0000

 

But shouldn't the value of both expressions be s:0000? Isn't the

LHS evaluated in 4-state then converted to 2-state?

 

Thanks,

 

Jason


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