Hi Jonathan. In verilog, a design unit is structurally part of the design. This would include a top-level module and all modules instantiated. The instantiations would be statements but not design units. I would view a package as a package of declarations which, even if it included design units, was not a design unit itself. I think an interface would not be a design unit, either. However, the "and", "or", etc. builtin primitives would be design units. This is just a verilog perspective. A "design unit" in sv could be extended further. However, I am not sure how confusing it might be to designers, to add packages to things included in "design units". One might share packages but would not design in them. Possibly, a "design unit" could be defined as the smallest unit in sv which could be simulated? This would eliminate classes, functions, and tasks . . .. jonathan.bromley@doulos.com wrote: >>> I believe that the lists of module, program, interface, >>> and checkers should include packages as well. >> Agreed. > > Did we ever get around to agreeing that the term > "design unit" covers all these? -- John Michael Williams Senior Adjunct Faculty Silicon Valley Technical Institute -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Oct 16 11:12:44 2009
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