Re: [sv-bc] RE: associativity of ** operator

Verilog-AMS had only the pow() operator -- where associativity was
not an issue -- until LRM 2.3, where the ** operator was added,
along with $math_functions ($exp, $sin), in accordance with Verilog.

When was ** added to 1364/1800?  Was associativity even considered?

-Geoffrey


Marq Kole wrote:
> Hi Steven, Shalom,
> 
> It's not a language incompatibility as Verilog-AMS also uses left associativity for this operator. I brought it up because of inconsistencies between the Verilog group of language and other programming languages that support the exponentiation operator, and the degeneration to single exponentiation with a left associative exponentiation operator.
> 
> I'm quite sure that changing this will break very little code, especially due to the degeneration - if you really wanted exponentiation of exponentiation to happen you are with the current standard forced to use parentheses.
> 
> Cheers,
> Marq
> 
> 
> Marq Kole
> Product Manager AMSRF Simulation
> NXP Semiconductors / Corporate I&T / Design Technology & Flows
> 
> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com] 
> Sent: Tuesday 27 October 2009 7:19
> To: Marq Kole; verilog-ams@eda.org; shalom.bresticker@intel.com
> Cc: sv-bc@eda.org
> Subject: Re: [sv-bc] RE: associativity of ** operator
> 
> 
>> From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> 
>> I also don't see why you think that with left-to-right associativity it becomes 
> equivalent to * except for the left-most operator. If that were the case, then 
> 2**3**2 would give you (2**3)*2 = 16, not 64.
> 
> He means that (2**3)**2 is equivalent to 2**(3*2).  If you left-associate
> your exponentiation, you get the same result as multiplying all of the
> exponents and then exponentiating once.
> 
> I believe that other languages like FORTRAN right-associate exponentiation,
> and that one reason is that if you meant to left-associate, you could have
> just used multiplication.  That still takes one set of parentheses, but
> forcing right-association with a left-associative convention takes a set
> of parentheses for each exponent.  I might have brought this up back when
> exponentiation was added to Verilog.
> 
> 
> 
>> In these programming languages, it is a matter of definition.
>>
>> In any case, changing the associativity now would cause a problem of backwards 
> compatibility, which is the main reason it won't be changed in SystemVerilog 
> (There won't be any more 1364 as it has been merged into SystemVerilog.).
> 
> 
> Since Verilog-AMS probably took its conventions from SPICE, which probably
> took them from FORTRAN, it probably right-associates.  So this would be
> an incompatibility between the languages.
> 
> 
> Steven Sharp
> sharp@cadence.com
> 
> 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.