[sv-bc] Query related with explicit name port declaration.

Hello,

I have a query related with  explicit name port declaration.

For example

module mod(output logic .P1(r));
   int  r;
endmodule

In above testcases once a type is specified with port then is this(logic 
here) will be regarded
as type of  "r" ??

If yes then does the redefinition of variable "r" should be treated as 
illegal as the name
is previously declared.

If not then what is the significance of specifying explicit data 
type(logic here) with port .

Different standard tools are behaving in  different way.

Regards,
dhiRAj




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