RE: [sv-bc] Query related with associative array assignment.

I think "same type" here should mean "matching type", as 6.22 in 1800-2009 says,

"Some constructs and operations require a certain level of type compatibility for their operands to be legal.
There are five levels of type compatibility, formally defined here: matching, equivalent, assignment compatible, cast compatible, and nonequivalent.

SystemVerilog does not require a category for identical types to be defined here because there is no construct in the SystemVerilog language that requires it. For example, as defined below, int can be interchanged with bit signed [31:0] wherever it is syntactically legal to do so."

So "matching" is the highest level of type compatibility.

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Dhiraj Kumar Prasad
> Sent: Thursday, November 26, 2009 5:22 AM
> To: sv-bc@server.eda.org
> Cc: Dhiraj Kumar Prasad
> Subject: [sv-bc] Query related with associative array assignment.
> 
> Hello,
> 
> I have a query related with associative array assignment.
> 
> According to LRM P1800-2005,section 5.11
> 
> "Associative arrays can be assigned only to another 
> associative array of 
> a compatible type and with the
>  same index type."
> 
> So same type don't include equivalent type??
> 
> Does the following testcase should pass ??
> 
> Testcase
> -------
> 
> module top();
> 
> typedef bit signed [31:0] bit32;
> bit var1[][bit32];
> bit var2[][int];
> 
> initial
>     var1 = var2;
> endmodule
> 
> As different standard simulator's are behaving in different way.
> 
> Regards,
> dhiRAj
> 
> 
> 
> 
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