Surya, I agree this was an oversight, but if you make the proposed correction, you need to make sure there is a semantic restriction that prevents a default assignment to a ref port. Dave > -----Original Message----- > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On > Behalf Of Surya Pratik Saha > Sent: Tuesday, December 01, 2009 3:49 AM > To: sv-bc@eda.org > Subject: [sv-bc] Should Ref declaration not use > list_of_variable_port_identifiers > > Hi, > In the SV 1800-2009-draft 7a LRM, the ref declaration rule is defined as: > > ref_declaration ::= ref variable_port_type list_of_port_identifiers > > But I think, it should use list_of_variable_port_identifiers so that > following example becomes legal: > > module top(x); > ref logic x[$]; > endmodule > > If this is an oversight of LRM then I will file a Mantis for that. > > -- > Regards > Surya > > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Dec 1 06:37:23 2009
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