Packages are the same as modules. I mentioned in October that packages are missing in the list. In 1800-2009, checkers are also in the list. Also, the use of an 'automatic' lifetime qualifier does not turn the module, interface, or package itself into automatic, in contrast to tasks and functions. Shalom ________________________________ From: Dhiraj Kumar Prasad [mailto:dhiraj@cal.interrasystems.com] Sent: Wednesday, December 02, 2009 8:55 AM To: Bresticker, Shalom Cc: sv-bc@server.eda.org; Surya Pratik Saha Subject: Re: [sv-bc] Query related with life time of variable declared inside automatic module/interface. Hello Shalom, Thanks for your reply. One more query related with package with life time in draft P1800-2009, the behavior for the variable declared inside automatic package should be same as that of module /interface/program or like task/function. Regards, dhiRAj Bresticker, Shalom wrote: The LRM wording is quite deliberate. The lifetime qualifier of modules and interfaces does not affect variables declared outside subroutines and code blocks. The LRM has this additional text, "An optional qualifier can be used to specify the default lifetime of all variables declared in a task, function, or block defined within a module, interface, package, or program. The lifetime qualifier is automatic or static. The default lifetime is static. program automatic test ; int i; // not within a procedural block - static task t ( int a ); // arguments and variables in t are automatic ... // unless explicitly declared static endtask endprogram" Shalom -----Original Message----- From: owner-sv-bc@server.eda.org<mailto:owner-sv-bc@server.eda.org> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Dhiraj Kumar Prasad Sent: Wednesday, December 02, 2009 8:07 AM To: sv-bc@server.eda.org<mailto:sv-bc@server.eda.org> Cc: Dhiraj Kumar Prasad; Surya Pratik Saha Subject: [sv-bc] Query related with life time of variable declared inside automatic module/interface. Hello, I have query regarding the lifetime of variable declared inside the automatic module/interface. According to LRM P1800-2005,section 6.6 "SystemVerilog data declared inside a module or interface, but outside a task, process, or function, are local in scope and static in lifetime (exist for the lifetime of the module or interface). This is roughly equivalent to C static data declared outside a function, which is local to a file." But don't say anything about the lifetime of variable when it's declared inside automatic module/interface. The above section should be consider both for static and automatic lifetime or it's oversight as different standard simulator are behaving in different way for the following testcase. Testcase --------- module automatic top(output int out1); bot I1(out1);//treating out1 as automatic so showing error for continuous assignment on automatic variable. endmodule module bot(output int out1); endmodule Regards, dhiRAj --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Dec 2 08:47:39 2009
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