Re: [sv-bc] 'force' strength

Here is a simpler answer than Gord's:

Based on the behavior of Verilog-XL, the resulting strength of a force is
the usual default of "Strong". If you print the forced net with the %v
format, you will see Str0, Str1 or StrX. And it will affect nets on the other
side of switch primitives as if it were strong (though you can't actually
tell based on that whether it is strong or supply, since supply reduces to
strong through a switch).

Unless of course you force a Z value, in which case it has a HiZ strength.

Steven Sharp
sharp@cadence.com

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.