RE: [sv-bc] changing the lifetime of begin end block

One simulator that I tested indeed behave as you say, but another flagged both x and y.
Note that the text says that the qualifier specifies the "default" lifetime.
If the lifetime is explicitly specified in the variable declaration, no default is involved.

Here is a fuller version of the text:

An optional qualifier can be used to specify the default lifetime of all variables declared in a task, function, or block defined within a module, interface, package, or program. The lifetime qualifier is automatic or static. The default lifetime is static.

program automatic test ;

int i; // not within a procedural block - static

task t ( int a ); // arguments and variables in t are automatic

... // unless explicitly declared static

endtask

endprogram

Note that the example shows the lifetime specified in the program declaration, and i is static only because it is not in a procedural block.

Shalom

________________________________
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Surya Pratik Saha
Sent: Thursday, February 11, 2010 1:14 PM
To: Bresticker, Shalom
Cc: Daniel Mlynek; sv-bc@eda.org; 'Bartek Konik'
Subject: Re: [sv-bc] changing the lifetime of begin end block

Hi,
I don't think, 'a' is automatic. The quoted text
"An optional qualifier can be used to specify the default lifetime of all variables declared in a task, function, or block defined within a module, interface, package, or program. The lifetime qualifier is automatic or static."
is actually talking about the declaration time qualifier of variable like "automatic int x;" etc.

Consider the following case:

module automatic bot;
bit clk;
task t;
    int y;
endtask
initial begin:b
    int x;
end
endmodule

module top;
    bot b();
    initial begin
        b.clk = 1; // This hierarchical reference is legal as 'clk' is not automatic
        b.b.x = 1; // This hierarchical reference is legal as 'x' is not automatic
        b.t.y = 1; // This hierarchical reference is illegal as 'y' is automatic
    end
endmodule

I have confirmed this with a standard simulator.

Regards
Surya

-------- Original Message --------
Subject: Re:[sv-bc] changing the lifetime of begin end block
From: Bresticker, Shalom <shalom.bresticker@intel.com><mailto:shalom.bresticker@intel.com>
To: Daniel Mlynek <daniel.mlynek@aldec.com.pl><mailto:daniel.mlynek@aldec.com.pl>, sv-bc@eda.org<mailto:sv-bc@eda.org> <sv-bc@eda.org><mailto:sv-bc@eda.org>
Cc: "'Bartek Konik'" <Bartek.Konik@aldec.com.pl><mailto:Bartek.Konik@aldec.com.pl>
Date: Thursday, February 11, 2010 4:26:57 PM
No.

The statements of the type, "The xxx defines the following" are more informative than normative. They are not necessarily complete. There is no contradiction. The statement does not say that the lifetime qualifier does not affect procedural blocks. It just does not mention them. There is not even a parallel statement, "The xxx header defines the following" for interfaces, programs, or packages.

But there is no problem to modify the statement to refers to procedural blocks as well as subroutines.

Shalom

________________________________
From: Daniel Mlynek [mailto:daniel.mlynek@aldec.com.pl]
Sent: Thursday, February 11, 2010 12:36 PM
To: Bresticker, Shalom; sv-bc@eda.org<mailto:sv-bc@eda.org>
Cc: 'Bartek Konik'
Subject: RE: [sv-bc] changing the lifetime of begin end block

Well I'm confused. IMO both statement cited below are in contradiction.

DANiel

________________________________
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Thursday, February 11, 2010 11:29 AM
To: Daniel Mlynek; sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: RE: [sv-bc] changing the lifetime of begin end block

Hi,

6.21 says,
"An optional qualifier can be used to specify the default lifetime of all variables declared in a task, function, or block defined within a module, interface, package, or program. The lifetime qualifier is automatic or static."

So a is automatic.

Regards,
Shalom

________________________________
From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Daniel Mlynek
Sent: Thursday, February 11, 2010 12:22 PM
To: sv-bc@eda.org<mailto:sv-bc@eda.org>
Subject: [sv-bc] changing the lifetime of begin end block

LRM1800-2009 adds new statement to the desc of module header:
 "The module header defines the following: - The default lifetime (static or automatic) of subroutines defined within the module"

My questiion is if default lifetime for module should be deafult only for subroutines declared inside such module or also to block declared in this module - see below example:

module automatic top;
bit clk;
initial repeat (10) #10 clk = ~clk;
always @(clk)
begin
     int a = 0; //<<<<this variable should be static or atuomatic???
    $display(a);
    a++;
end
endmodule

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