[sv-bc] Re: [sv-ac] SV-AC feedback for the next PAR

On checkers, also
. Allow in the checker declaration the use of the "if" and "case" statement
example:
checker c (...);
  if(a) ap_P1: assert property(...);
endchecker c

On Mon, Feb 15, 2010 at 5:30 AM, Korchemny, Dmitry <
dmitry.korchemny@intel.com> wrote:

> Hi all,
>
> Here is the list of enhancements that I suggest for the coming PAR. Though
> all suggested enhancements are targeted for assertions, some of them are
> generic, and do not belong to assertions only. Therefore, I am sending this
> proposal also to SV-BC and SV-EC.
>
> Checkers
> Remove or relax restrictions imposed on checkers:
> * Allow checker instantiation in functions and tasks
> * Allow checker instantiation in classes
> * Allow output arguments in checkers
> * Allow design variable forcing from checkers
> * Allow continuous assignments in checkers
> * Allow procedural control and looping statements in checkers
> * Refine definition of checker argument sampling
>
> Multiple Arguments
> Support variable number of arguments in SV constructs: macro, assertions,
> and checkers. Since this mechanism is generic, it makes sense to expand it
> also to modules, interfaces, programs, functions, and tasks.
>
> Types
> Introduce a generic integral type and provide explicit means to check type
> cast compatibility
> * Introduce generic type integral (the name is tentative) to specify
> any integral type in arguments of assertions and checkers.
> * Introduce a system function with two arguments that are type
> expressions, returning true if the first type expression is cast-compatible
> with the second one.
>
> Bit-vector System Functions
> Clarify usage of existing bit-vector functions ($onehot, etc.) and
> introduce new ones
> * State explicitly that the argument of bit-vector functions may be
> unpacked
> * Introduce bit-vector system functions for efficient work with
> 4-valued data types
>
> AMS Assertions (tentative)
> Enhance SVA with AMS assertions. This requires merging SV and VerilogAMS.
>
> Temporal Coverage (tentative)
> Bridge gap between SVA and SV functional coverage by introducing temporal
> coverage.
>
> I filled a new Mantis 2979 where I uploaded a presentation containing
> examples and motivation. The solution directions and the syntax proposed in
> the presentation do not necessarily address all the aspects of the language,
> and they are provided for illustration purposes only.
>
> Thanks,
> Dmitry
>
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Thomas
> Thatcher
> Sent: Thursday, February 11, 2010 3:50 AM
> To: sv-ac@eda.org
> Subject: [sv-ac] SV-AC feedback for the next PAR
>
> Hello Everyone,
>
> We need to give feedback to the working group on the scope of the next
> PAR, which will be discussed at the next working group. Anyone who has
> suggestions about assertion-related enhancements to be worked on in the
> next PAR should send them to the SV-AC alias. I will attempt to compile
> a prioritized list to present to the working group.
>
> Thanks,
>
> Tom
>
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