Subject: $sv-ec Re: SV_EC September4,02 testbench discussion presentation
From: Francoise Martinolle (fm@cadence.com)
Date: Thu Sep 05 2002 - 15:38:13 PDT
Thanks to Medhi for doing the presentation and not only proactively looking
at the conflicts between SV and VERA but also proposing resolutions. The
presentation
helped me to understand the differences between SV and VERA and the testing
features that VERA supports. I think that VERA has some valuable concepts;
in particular I like the semaphores and mailboxes (even though I would
prefer to see them implemented as classes).
After the meeting as I was flying back to Boston, I spent some time
thinking about how would VERA fit in systemVerilog. In order to do that I
felt that I needed to step back and
think about the objectives and use of a testbench language in order to
evaluate if VERA would be a suitable donation.
First I would like to raise some questions around the language requirements
for systemVerilog. I apologize if this was discussed before as I am not
aware of it and I could not find anything on it in the email threads on
this working group. Please point me to
a requirement document if one exists, otherwise can someone try to answer
my questions?
These answers will guide me to picture and judge how we can design a
language which can be adequate for testing and hardware design.
1. Is it necessary for a hardware description language which is used for
design to contain language constructs for testing?
Should SV contain everything for testing purpose, or should SV only
contain provision to
integrate easily with a testbench program?
2. would the engineer who uses SV for designing his system also be the same
engineer who writes the tests?
3. Should'nt a testbench language be HDL independent?
note: VERA has many language independent features (classes, lists, process
threads...) modifying VERA syntax and semantics to fit within SV may
conflict with that requirement.
4. Shouldn't the testbench program/module be completely separated from the
HDL design?
If not, what are the advantages of embedding the tests in the design?
I see the disadvantage that it would require the design to be
recompiled every time I
want to use a new test program.
5. What are the various kinds/types/scenarios of tests that one may want to
do and that the language should support? Do they have different scope?
6. VHDL and Verilog and also PLI have been used for writing testbenches,
what were their weaknesses and strengths in their testing capabilities?
Is SV or VERA addressing these?
There may be more questions but these are the first ones which came up to me.
I would really appreciate if some people could share their opinions and provide
some answers to my questions.
Francoise
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