Subject: RE: $sv-ec Re: SV_EC September4,02 testbench discussion presentat ion
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Sep 06 2002 - 08:44:20 PDT
Hello Francoise,
This has been discussed in the TCC as well as in a full committee of
HDL+.
SystemVerilog 3.0 standard provides many construct that you can find
in many testbench language of today. We did not associate it with a
particular testbench language. You can make an exercise and find many
commonality. Originally Verilog when it was first introduced, many people
were used to gate level, and tabular 1,0 for testbench. Designers discovers
that they can write testbench in a procedural manner using Verilog which
helped to improve Verification of design as it grew in complexity. The
testbench features of SystemVerilog 3.0 should be enhanced to allow better
flexibility for designers and verification.
EDA industry and users elected to create a separate language to do a
testbench. Verilog was not enhanced in the proper way to improve its
testbench capability. There is no golden rule, that says that testbench
language should be a different language than a design language. Please note
that Verilog is NOT just a design language but also a verification language.
Now if you examine Verilog, which part of it you can say it is verification
or which is part of it design.
If you examine OVL, powerful concept of verification libraries,
created by Harry Foster using Verilog Language. The use of OVL helps
designers to check his design quickly using simulation. This is advanced
aspect of Verification.
As part of Accellera roadmap, we have created HDL+ (the goal for
this large committee to create advanced verification and design languages
that is built on existing hardware languages. We have started with Verilog.
That is why you find OVL committee and SystemVerilog committees under this
HDL+. SystemVerilog 3.0 contained assertions by design and by Accident. the
TCC vision is to make SystemVerilog 3.1 to contain better verification
technology. This is not just confined to assertion, but we also like to see
advanced testbench capability to be added.
By providing SystemVerilog 3.1, we are hoping to see better tools
that can take advantage of the several concepts that will be provided in
this version. Your example of semaphores and mailboxes can be used by
hardware and software model interactions. The designers can use these
concept to build an embedded system. We also envision tools that can
generate functional vectors automatically. It will be beneficial for
designers to see this testbench in SystemVerilog language. There is also
intelligent verification which many advanced EDA companies are working on.
Please remember OVL, in terms of embedding smart assertion in the
design to help in the verification. Testbench monitors, checkers and others
can be really built like OVL using these testbench concept. Designers or
verification engineers can these testbench verification libraries, EMBEDDED
in the design to help deliver good quality but also deliver IP verification
modules in SV.
Associated with the these enhancements are also enhancement in C/API
for SystemVerilog.
We need to get out of traditional thinking and explore how to
improve verification. As a final note, whatever additions we add for
verification, there is no limit, why it cannot be used for design.
I hope that these provided Accellera TCC HDL+ vision and why we have
created all of those activities to help improve design and verification. We
have debated the name of HDL+ or HDVL+.
Best Regards
Vassilios
-----Original Message-----
From: Francoise Martinolle [mailto:fm@cadence.com]
Sent: Friday, September 06, 2002 12:38 AM
To: Mehdi Mohtashemi; sv-ec@eda.org
Subject: $sv-ec Re: SV_EC September4,02 testbench discussion
presentation
Thanks to Medhi for doing the presentation and not only proactively looking
at the conflicts between SV and VERA but also proposing resolutions. The
presentation
helped me to understand the differences between SV and VERA and the testing
features that VERA supports. I think that VERA has some valuable concepts;
in particular I like the semaphores and mailboxes (even though I would
prefer to see them implemented as classes).
After the meeting as I was flying back to Boston, I spent some time
thinking about how would VERA fit in systemVerilog. In order to do that I
felt that I needed to step back and
think about the objectives and use of a testbench language in order to
evaluate if VERA would be a suitable donation.
First I would like to raise some questions around the language requirements
for systemVerilog. I apologize if this was discussed before as I am not
aware of it and I could not find anything on it in the email threads on
this working group. Please point me to
a requirement document if one exists, otherwise can someone try to answer
my questions?
These answers will guide me to picture and judge how we can design a
language which can be adequate for testing and hardware design.
1. Is it necessary for a hardware description language which is used for
design to contain language constructs for testing?
Should SV contain everything for testing purpose, or should SV only
contain provision to
integrate easily with a testbench program?
2. would the engineer who uses SV for designing his system also be the same
engineer who writes the tests?
3. Should'nt a testbench language be HDL independent?
note: VERA has many language independent features (classes, lists, process
threads...) modifying VERA syntax and semantics to fit within SV may
conflict with that requirement.
4. Shouldn't the testbench program/module be completely separated from the
HDL design?
If not, what are the advantages of embedding the tests in the design?
I see the disadvantage that it would require the design to be
recompiled every time I
want to use a new test program.
5. What are the various kinds/types/scenarios of tests that one may want to
do and that the language should support? Do they have different scope?
6. VHDL and Verilog and also PLI have been used for writing testbenches,
what were their weaknesses and strengths in their testing capabilities?
Is SV or VERA addressing these?
There may be more questions but these are the first ones which came up to
me.
I would really appreciate if some people could share their opinions and
provide
some answers to my questions.
Francoise
'
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