$sv-ec References in SystemVerilog (proposal)


Subject: $sv-ec References in SystemVerilog (proposal)
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Wed Sep 18 2002 - 19:53:27 PDT


I'm not sure if there is an official donation for references or not, 'var' appeared in some
of the Testbench discussion - but I had trouble tracking down the text. SuperLog has
some ref/deref stuff that was not donated. Either of those approaches introduce new
keywords and are a little unwieldy. I'd like to propose something more along the lines
of C++'s & reference operator - using operators instead of keywords. E.g.:

    int table[15:0],
                   &pt; // pt is an integer reference
    ....
        pt &= table[5]; // pt becomes a reference to table entry 5
        ...
        pt = 12; // table[5] becomes 12

Since '&' is not valid as an identifier name and expressions are not expected in that context,
there is no clash with its other uses. The assignment operator "&=" can be read as "refers to"
and is similar to " = & " in C. No dereference operator is required, new operators can be
added to manipulate the reference e.g.:

        pt &++; // increment reference to next element
        pt &--; // decrement

        pt &+= shift; // move reference by shift
        pt &-= shift; // ditto -shift

        pt &= null; // invalidate.

An out of range assignment would be the same as a null assignment, comparison operators
would allow for checking:

        if (pt &== null) begin...

        if (pt &!= table[3]) begin // skip special entry
         ....

Using a null reference would be a runtime error, and references would be initially null.
A reference can be used with "new" to create new objects e.g.:

        int &pi[4:0]; // pi is a reference to 5 int array
        initial begin
            pi &= new; // create a 5 int array
            pi[0] = 1;
            ....

A "destroy" method is not required as the object will be reclaimed automatically when
no references exist.

The '&' can be used in task/function call argument lists to indicate pass-by-reference.

        task foo (output int bar, input integer &data[1023:0]);
            ...

References can be written to channels (of the reference type), e.g.:

        typedef int pckt[0:255];
        channel pckt dut_data; // data channel to hardware
        typedef pckt &pp;
        channel pp ref_data; // channel to test-bench
        ...
        @(send_pkt) begin
            pp &= new;
            init_pckt(pp); // fix data
            dut_data <= pp; // send data to DUT
            ref_data <&= pp; // send reference to checker
        end

Note: each iteration of the loop above creates a new packet object which exists until
all references to it are destroyed, i.e. it will exist until the reference written to the ref_data
channel is read and discarded.

-----------------------

If the text isn't in the right form for official consideration I'll rewrite it. Feedback appreciated
in the interim.

Regards,
Kev.



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