Subject: Re: $sv-ec References in SystemVerilog (proposal)
From: Steven Sharp (sharp@cadence.com)
Date: Tue Sep 24 2002 - 11:42:05 PDT
I would like to point out some serious issues with trying to add pointers
to Verilog. Verilog variables are not simple storage locations that you
can just write to, like variables in most other languages (including C and
VHDL). They have a lot of extra semantics already defined for them. They
can have fanout that has to be notified any time the value changes. They
can have procedural continuous assigns and forces applied to them, which
prevent any other writing to them.
Any write to a Verilog variable via a reference type is going to have to
handle all of this properly and efficiently. That rules out any kind of
simple pointers that are just addresses of data storage and can be
manipulated arithmetically, like in C. Off the top of my head, I can see
a few ways of trying to deal with this:
1. Define a new type of variables that act like variables in other
languages, and don't allow the full functionality of existing Verilog
variables. Only allow pointers to variables of this type.
2. Severely restrict what can be done with reference types so that the
system can easily keep track of what object any reference object refers
to. For example, no pointer arithmetic. The same restrictions should
help avoid some of the bugs that come up with unrestricted pointers, and
which many hardware engineers will not be familiar. Note that even these
restricted reference types would kill many optimizations on any object
that might be referenced.
3. Turn all reference types into more complex descriptors that keep track
of what object they reference plus an address somewhere in the storage for
the object. This requires extra work for every operation involving the
reference type, slowing down simulation. This is in addition to the other
effects on optimizations.
Steven Sharp
sharp@cadence.com
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