Subject: Re: $sv-ec Aliases
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Wed Oct 16 2002 - 15:07:07 PDT
Adam Krolnik wrote:
> Hi Kevin;
>
> Since verilog allows statements like:
>
> assign
> a = b,
> c = d,
> e = f;
>
> Should alias not have the same syntax capabilities?
>
> Since verilog does not allow statements like:
>
> a = b = c = d + 1;
>
> Should alias not follow the same restrictions? E.g. strike
> the optional { = <net_lvalue> } and instead require two
> x = y statements?
>
> alias
> a = b,
> b = c
> c = d;
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
The reason for using "," instead of "=" originally was that it isn't
really any
kind of assignment - it's more like a union. From a user perspective,
the list
syntax saves repeating elements - and I think in general that leads to
fewer
accidental errors.
The list syntax makes slightly more sense if you have the '?' don't-care
syntax
since you can have more members in the list more easily.
Note: I would still like to have some don't-care/no-connection for
padding
alias and packed union members - otherwise users will add redundant
signals
and fields to do the job.
Kev.
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