Subject: Re: $sv-ec Aliases
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Oct 16 2002 - 14:07:09 PDT
Hi Kevin;
Since verilog allows statements like:
assign
a = b,
c = d,
e = f;
Should alias not have the same syntax capabilities?
Since verilog does not allow statements like:
a = b = c = d + 1;
Should alias not follow the same restrictions? E.g. strike
the optional { = <net_lvalue> } and instead require two
x = y statements?
alias
a = b,
b = c
c = d;
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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