Subject: Re: $sv-ec Aliases
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Wed Oct 16 2002 - 10:24:11 PDT
New version, using "=" no don't-cares and limited semantics.
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BNF ~:
<alias_statement> ::== alias <net_lvalue> = <net_lvalue>{ = <net_lvalue>}
The LRM text would be:
X.Y Signal Aliasing
The SystemVerilog assign statement is a unidirectional assignment and may incorporate a delay and
strength change. To model a bidirectional short-circuit connection it is necessary to use the alias
statement. The members of an alias list are signals whose bits share the same physical wires.
The example below implements a byte order swapping between bus A and bus B.
module byte_swap (inout A, inout B);
wire [31:0] A,B;
alias {A[7:0],A[15:8],A[23:16],A[31:24]} = B;
endmodule
This example strips out the least and most significant bytes from a four byte bus:
module byte_rip (inout W, inout LSB, inout MSB);
wire [31:0] W;
wire [7:0] MSB,LSB;
alias W[7:0] = LSB;
alias W[31:24] = MSB;
endmodule
The bit overlay rules are the same as those for a packed union with the same member types: each
member should be the same size and connectivity is independent of the simulation host.
Any net data types can be used in an alias list as long as the resulting connections do not violate
the rules for net connection that would apply if the nets were being joined at a port, reg data
types cannot be aliased. The same nets can appear in multiple alias statements, the effects are
cumulative. The following two examples are equivalent, in either case low12[11:4] and
high12[7:0] will share the same wires:
module overlap(inout bus16, inout low12, inout high12);
wire [15:0] bus16;
wire [11:0] low12,high12;
alias bus16[11:0] = low12;
alias bus16[15:4] = high12;
endmodule
module overlap(inout bus16, inout low12, inout high12);
wire [15:0] bus16;
wire [11:0] low12,high12;
alias bus16 = {high12,low12[3:0]};
alias high12[7:0] = low12[11:4];
endmodule
To avoid errors in specification it is not allowed to specify an alias from an individual signal to
itself or to specify a given alias more than once, so the following version of the code above
would be illegal since the top four and bottom four bits are the same in both statements:
alias bus16 = {high12[11:8],low12};
alias bus16 = {high12,low12[3:0]};
Using a net in an alias statement does not modify it's syntactic behavior in other statements.
Aliasing is performed at elaboration time and cannot be undone.
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Note: without the restrictions in the 2nd last paragraph you could write:
alias bus16 = {high12,bus16[3:0]} // signals aliased to self
= {bus16[15:12],low12};
or
alias bus16 = {high12,low12[3:0]}
= {high12[11:8],low12}; // specifies top and bottom 4 bits twice
Not aliasing a signal to itself just applies to single wires so the following is OK:
alias bus16[1] = bus16[2]; // short low order bits
These restrictions are just a suggestion, Stu can strike that paragraph if nobody else
thinks it's a good idea.
Regards,
Kev.
-- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
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