Subject: $sv-ec Aliases
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Sep 16 2002 - 13:11:16 PDT
[Previously: http://www.eda.org/vlog-pp/hm/0315.html]
The reasons for an "alias" statement are:
a) To replace the "jumpered port" syntax.
b) To replace bus-ripping (zero-delay) assigns which are meant to be short-circuits
in the hardware. This is very important for Verilog-A[MS] which may auto-insert
A/D converters inappropriately.
The previous proposal was to add a keyword "alias" with a list of aliased items,
since it is actually a kind of union you could skip adding a keyword and use (say)
"assign packed union" e.g.:
module foo (output a, input b[3:0])
reg a;
wire b[3:0];
assign packed union {a;
b[0];}; // short a & b[0]
BNF ~:
<alias_statement> ::== assign {packed} union "{"<net_lvalue>;<net_lvalue>{;<net_lvalue>}"}"
The LRM text would be:
X.Y Signal Aliasing
The SystemVerilog assign statement is a unidirectional assignment and may incorporate a delay and
strength change. To model a bidirectional short-circuit connection it is necessary to use the "assign
union" statement. The members of an assign union are signals whose bits share the same physical wires.
The example below implements a byte order swapping between bus A and bus B.
module byte_swap (inout A, inout B);
wire [31:0] A,B;
assign packed union {{A[7:0],A[15:8],A[23:16],A[31:24]};
B;}
endmodule
The assign union can be packed or unpacked, the bit overlay rules are the same as those for a union
with the same member types.
--Regards, Kev.
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