Subject: Re: $sv-ec Aliases
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Oct 03 2002 - 11:06:25 PDT
Updated version, reverting to "alias" keyword, list syntax and fuller semantics to
address questions from last meeting -
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BNF ~:
<alias_statement> ::== alias <net_lvalue>,<net_lvalue>{,<net_lvalue>}
The LRM text would be:
X.Y Signal Aliasing
The SystemVerilog assign statement is a unidirectional assignment and may incorporate a delay and
strength change. To model a bidirectional short-circuit connection it is necessary to use the alias
statement. The members of an alias list are signals whose bits share the same physical wires.
The example below implements a byte order swapping between bus A and bus B.
module byte_swap (inout A, inout B);
wire [31:0] A,B;
alias {A[7:0],A[15:8],A[23:16],A[31:24]},
B;
endmodule
The bit overlay rules are the same as those for a packed union with the same member types, so
connectivity is independent of the simulation host. Any net data types can be used in an alias list
as long as the resulting connections do not violate the rules for net connection that would
apply if the nets were being joined at a port. As with packed unions all bits must be specified
in each list member, if a partial alias is required the unused bits can be indicated with '?' as
in the following example:
module ls_byte_rip (inout W, inout B);
wire [31:0] W;
wire [7:0] B;
alias A,{24{?},B};
endmodule
It is valid to alias reg data types in the same module, and the effect is the same as if they
had been declared in seperate modules and joined through ports i.e. two seperate drivers are
created and their values are resolved to give the alias value:
module reg_alias(input In,input hold,output Out)
reg X,Y;
wire hold,
Out; // the resolved value of X and Y
alias X,Y,Out;
always @(posedge In) X <= hold ? In : 1'bZ;
always @(negedge In) Y <= hold ? In : 1'bZ;
endmodule
Using a net or reg type in an alias statement does not modify it's syntactic behavior in other
statements. Aliasing is performed at elaboration time and cannot be undone.
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Feel free to offer better examples and/or syntax/semantics.
Regards,
Kev.
------
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