$sv-ec Proposal for Random Constraints for SV-extension

Subject: $sv-ec Proposal for Random Constraints for SV-extension
From: Mehdi Mohtashemi (Mehdi.Mohtashemi@synopsys.com)
Date: Mon Nov 18 2002 - 14:07:06 PST

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David, all,

 Please find the attached [ .pdf ] document titled, Random Constraints - Proposal,
for the systemVerilog 3.1. This proposal is in reference to the Accellera SV-EC
Extension Proposals titled: 'Constraints/Randomization'.

Please let me know if there are any problems with viewing the file.
Regards,
- Mehdi Mohtashemi
  Synopsys, Inc.
  mehdi@synopsys.com

• application/pdf attachment: Random-Constraints_Proposal.pdf

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