Subject: Re: $sv-ec alias proposal comments
From: Shalom.Bresticker@motorola.com
Date: Tue Nov 19 2002 - 02:55:17 PST
On Mon, 11 Nov 2002, Kevin Cameron x3251 wrote:
> > Example:
> > module alias (a, a)
> > inout [WIDTH:0] a;
> > endmodule
> >
> > Then instantiate it in module top to alias b and {c,d} together:
> > module top
> > wire [15:7] b;
> > wire [7:4] c;
> > wire [3:0] d;
> >
> > alias #7 u1( b, {c, d});
> > end module
>
> > The only thing I would like to specify in your proposal is what the resolved net type when
> > the net aliased together have diffent net types.
> > For example, you could have a tri0 wire aliased to a wand wire. What is the resulting inout
> > net type?
>
> The proposal says that aliasing nets is much the same as if they had been joined through
> ports - i.e. the same rules apply and the resulting net type would be the same.
What would be 'external' and what would be 'internal'?
>
> > The net type resolution table in the Verilog 1364 LRM (section 12.3.10 in the 1364 -2001 standard
> > only deals with resolution of net types across ports and resolves it to either the external net type or
> > the internal net type and in some situations issue a warning. The resolution as stated in the LRM is
> > not a symmetrical relationship between external and internal: for example between tri0 and wand,
> > tri0 not always wins. The external type wins.
>
> For the sake of argument you can consider the alias statement as being eqivalent to a module instantiation
> (of the kind above) that has jumpered ports, the semantics should be the same.
In jumpered ports, you really have 3 entities: the two external connections to
the alias module and also the internal net type within the alias module.
Shalom
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