Subject: RE: [sv-ac] Re: $sv-ec Proposal for Random Constraints for SV-extension
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Nov 21 2002 - 09:35:03 PST
Hello Adam,
This proposal is actually a response to the requirment sent from Faisal
for random constraints. Before getting to detailed on syntax and
operators I think we need to make sure that the functionality defined in
the proposal matches up with the semantics required. If so, then clearly
we need to make sure that syntax becomes consistent.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Adam
Krolnik
Sent: Thursday, November 21, 2002 8:44 AM
To: Mehdi Mohtashemi
Cc: sv-ec@eda.org; sv-ac@eda.org
Subject: [sv-ac] Re: $sv-ec Proposal for Random Constraints for
SV-extension
Hi Mehdi;
You wrote:
"The type randc can be thought of as a short-hand for rand unique."
It may be better to have a longer-hand than 'randc' for this difference
in functionality. The keyword 'randc' is not visually distinct enough
from rand.
These proposed extensions have some overlap with assertions. The SV-AC
group has been talking about the fact that assumptions on a set of
inputs to a block can constitute a specification of constraints for
legal stimulus to be applied.
Maybe this proposal needs to be sync'd up with work that the SV-AC is
doing. For example, this proposal defines operators 'inside' and '=>',
both concepts which have been discussed in the SV-AC. It would be highly
useful to use common syntax.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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