Subject: $sv-ec Verilog-A Parameter Ranges
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Nov 25 2002 - 13:57:58 PST
Here's the range specification stuff from the Verilog-AMS 2.X LRM:
3.2.2 Value range specification
A parameter declaration can contain optional specifications of the permissible range of the values of a parameter. More than one range can be specified for inclusion or exclusion of values as legal values for the parameter.
Parameters Data types
The use of brackets, [ and ], indicate inclusion of the end points in the valid range. The use of parenthesis, ( and ), indicate exclusion of the end points from the valid range. It is possible to include one end point and not the other using [ ) and ( ]. The first expression in the range shall be numerically smaller than the second expression in the range.
Examples:
parameter real neg_rail = -15 from [-50:0) ;
parameter integer pos_rail = 15 from (0:50) ;
parameter real gain = 1 from [1:1000] ;
Here, the default value for neg_rail is -15 and it is only allowed to acquire values within the range of -50 <= neg_rail < 0. Similarly, the default value for parameter pos_rail is 15 and it is only allowed to acquire values within the range of 0 < pos_rail < 50. And, the default value for gain is 1 and it is allowed to acquire values within the range of 1<= gain <= 1000. The keyword inf can be used to indicate infinity. If preceded by a negative sign, it
indicates negative infinity.
Example:
parameter real val3=0 from [0:inf) exclude (10:20) exclude (30:40];
A single value can be excluded from the possible valid values for a parameter.
Example:
parameter real res = 1.0 exclude 0 ;
Here, the value of a parameter is checked against the specified range. Range checking applies to the value of the parameter for the instance and not against the default values specified in the device. It shall be an error only if the value of the parameter is out of range during simulation.
3.2.3 Parameter arrays
Verilog-AMS HDL includes behavioral extensions which utilize arrays. It requires these arrays be initialized in their definitions and allow overriding their values as with other parameter types. The declaration of arrays of parameters is in a similar manner to those of parameters and register arrays of reals and integers in IEEE 1364-1995 Verilog HDL. Parameter arrays have the following restrictions. Failure to follow these restrictions shall result in an error.
• A type of a parameter array shall be given in the declaration.
• An array assigned to an instance of a module shall be of the exact size of the array bounds of that instance.
• If the array size is changed via a parameter assignment, the parameter array shall be assigned an array of the new size from the same module as the parameter assignment that changed the parameter array size.
Example:
parameter real poles[0:3] = { 1.0, 3.198, 4.554, 2.00 };
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It would be easy (IMO) to add the ":=" weight syntax to the individual ranges as
in the "dist" syntax, and use the one syntax for ranges in all cases. I would prefer to
depracate "from" (and "inside") and use a seperate "range" declaration/keyword, e.g.:
range v_r = [0:inf) exclude (10:20) exclude (30:40];
parameter real val_1 = 1.5 range v_r;
range p_r = [0:2] := 5 or (2:inf) := 10; // split range with weights
parameter real val_1 = 3.0 range p_r;
Syntax needs work - AMS version is one range with multiple exclusions, need
multiple ranges for adding weights (I used 'or' in the example to do it). It would
probably be useful to be able to do things like:
range v_r = [0:inf);
parameter real val_1 = 1.5 range v_r exclude (10:20);
parameter real val_2 = 2.2 range v_r exclude (30:40];
Kev.
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